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date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 1 sp690a/692a/802l/ 802m/805l/805m low power microprocessor supervisory with battery switch-over the sp690a/692a/802l/802m/805l/805m are a family of microprocessor ( p) supervisory circuits that integrate a myriad of components involved in discrete solutions to monitor power- supply and battery-control functions in p and digital systems. the series will significantly improve system reliability and operational efficiency when compared to discrete solutions. the features of the sp690a/692a/802l/802m/805l/805m include a watchdog timer, a p reset and backup-battery switchover, and power-failure warning, a complete p monitoring and watchdog solution. the series is ideal for applications in automotive systems, computers, controllers, and intelligent instruments. all designs where it is critical to monitor the power supply to the p and it?s related digital components will find the series to be an ideal solution. features precision voltage monitor: sp690a/sp802l/sp805l at 4.65v sp692a/sp802m/sp805m at 4.40v reset time delay - 200ms watchdog timer - 1.6 sec timeout minimum component count 60 a maximum operating supply current 0.6 a maximum battery backup current 0.1 a maximum battery standby current power switching 250ma output in v cc mode (0.6 ? ) 25ma output in battery mode (5 ? ) voltage monitor for power fail or low battery warning available in 8 pin so and dip packages reset asserted down to v cc = 1v description r e b m u n t r a p t e s e r d l o h s e r h td l o h s e r h t d l o h s e r h t d l o h s e r h td l o h s e r h t t e s e r y c a r u c c ay c a r u c c a y c a r u c c a y c a r u c c ay c a r u c c a e v i t c a t e s e r y c a r u c c a i f p a 0 9 6 p sv 5 6 . 4v m 5 2 1w o l% 4 a 2 9 6 p sv 0 4 . 4v m 5 2 1w o l% 4 l 2 0 8 p sv 5 6 . 4v m 5 7w o l% 2 m 2 0 8 p sv 0 4 . 4v m 5 7w o l% 2 l 5 0 8 p sv 5 6 . 4v m 5 2 1h g i h% 4 m 5 0 8 p sv 0 4 . 4v m 5 2 1h g i h% 4 1 2 3 4 5 6 7 8 8 pin nsoic vout vcc gnd pfi vbatt reset (reset)* wdi pfo *sp805 only ? now available in lead free packaging pin compatible upgrades to max690a/692a/802l/802m/805l applications critical p power monitoring intellegent instruments computers controllers
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 2 absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifica- tions below is not implied. exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. v cc ........................................................-0.3v to 6.0v v batt .....................................................-0.3v to 6.0v all other inputs (note 1)..................-0.3v to (v cc to 0.3v) input current: v cc .........................................................250ma v batt ........................................................50ma gnd........................................................20ma output current: v out .....short-circuit protected for up to 10sec all other inputs................................ .20ma rate of rise, v cc ,v batt ................. .100v/ s continuous power dissipation.......500mw storage temperature.......-65 c to +160 c esd rating.............................................................4kv electrical characteristics v cc =4.75v to 5.50v for sp690a/sp802l/sp805l, v cc =4.50v to 5.50v for sp692a/sp802m/sp805m, v batt =2.80v, t a =t min to t max , typical specified at 25 o c, unless otherwise noted. s r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c , e g n a r e g a t l o v g n i t a r e p o05 . 5s t l o v v c c v r o t t a b 2 e t o n , i , t n e r r u c y l p p u s y l p p u s ,5 30 6 a i g n i d u l c x e t u o i y l p p u s , e d o m p u k c a b y r e t t a b n i v c c v , v 0 = t t a b v 8 . 2 = 1 0 0 . 06 . 0 a v t t a b 3 e t o n , t n e r r u c y b d n a t s1 . 0 - 2 0 . 0 a v c c v > t t a b v 2 . 0 + v t u o t u p t u ov c c 1 . 0 -v c c 3 0 . 0 - v c c 5 1 . 0 - s t l o v i t u o a m 0 5 = i t u o a m 0 5 2 = v t u o e d o m p u k c a b - y r e t t a b n i v c c v < t t a b v 2 . 0 - v t t a b 5 1 . 0 -v t t a b 4 0 . 0 - v t t a b 0 2 . 0 - s t l o v i t u o a m 5 = i t u o a m 5 2 = , d l o h s e r h t h c t i w s y r e t t a b v c c v o t t t a b 0 2 0 2 - v m p u - r e w o p n w o d - r e w o p s i s e r e t s y h r e v o h c t i w s y r e t t a b0 4v mk a e p o t k a e p d l o h s e r h t t e s e r0 5 . 4 5 2 . 4 5 5 . 4 0 3 . 4 5 6 . 4 0 4 . 4 5 7 . 4 0 5 . 4 0 7 . 4 5 4 . 4 s t l o v l 5 0 8 p s , l 2 0 8 p s , a 0 9 6 p s m 5 0 8 p s , m 2 0 8 p s , a 2 9 6 p s t , l 2 0 8 p s a v , c 5 2 + = c c g n i l l a f t , m 2 0 8 p s a v , c 5 2 + = c c g n i l l a f
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 3 s r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c s i s e r e t s y h d l o h s e r h t t e s e r0 4v mk a e p o t k a e p t , h t d i w e s l u p t e s e r s r 0 4 10 0 20 8 2s m , e g a t l o v t u p t u o t e s e rv c c 5 . 1 -i e c r u o s 0 0 8 = a 5 e t o n1 . 04 . 0s t l o vi k n i s a m 2 . 3 = 4 0 0 . 03 . 0i k n i s 0 5 = v , a c c 0 . 1 = , e g a t l o v t u p t u o t e s e r8 . 0i e c r u o s 4 = v , a c c , v 0 . 1 = 6 e t o nv c c 5 . 1 -s t l o vi e c r u o s 0 0 8 = a 1 . 04 . 0i k n i s a m 2 . 3 = t , t u o e m i t g o d h c t a w d w 0 0 . 10 6 . 15 2 . 2c e s t , h t d i w e s l u p i d w p w 0 5s nv l i v , v 4 . 0 = h i v ( ) 8 . 0 ( = c c ) , d l o h s e r h t t u p n i i d w v c c 4 e t o n , v 5 =5 . 3 8 . 0 s t l o v w o l c i g o l h g i h c i g o l t n e r r u c t u p n i i d w 0 5 1 - 0 5 0 5 - 0 5 1 a v = i d w c c v 0 = i d w d l o h s e r h t t u p n i i f p0 0 2 . 1 5 2 2 . 1 0 5 2 . 1 0 5 2 . 1 0 0 3 . 1 5 7 2 . 1 s t l o v m / l 5 0 8 p s , a 2 9 6 / a 0 9 6 p s m / l 2 0 8 p s t n e r r u c t u p n i i f p5 2 -1 0 . 05 2a n e g a t l o v t u p t u o o f pv c c 5 . 1 - 1 . 04 . 0 s t l o v i e c r u o s 0 0 8 = a i k n i s a m 2 . 3 = note 1: the input voltage limits on pfi (pin 4) and wdi (pin 6) may be exceeded if the current into these pins is limited to less than 10 ma. note 2: either v cc or v batt can go to 0v if the other is greater than 2.0v. note 3: "-" equals the battery-charging current, "+" equals the battery-discharging current. note 4: wdi is guaranteed to be in an intermediate, non-logic level state if wdi is floating and v cc is in the operating voltage range. wdi is internally biased to 35% of v cc with an input impedance of 50k ? . note 5: sp690a, sp692a, sp802l, and sp802m only. note 6: sp805l and sp805m only. note 7: wdi minimum rise/fall time is 2 s. electrical characteristics v cc =4.75v to 5.50v for sp690a/sp802l/sp805l, v cc =4.50v to 5.50v for sp692a/sp802m/sp805m, v batt =2.80v, t a =t min to t max , typical specified at 25 o c, unless otherwise noted. note 7
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 4 pin assignments pin 1 ? out ?output supply voltage. v out connects to v cc when v cc is greater than v batt and v cc is above the reset thresh- old. when v cc falls below v batt and v cc is below the reset threshold, v out connects to v batt . connect a 0.1 f capacitor from v out to gnd. pin 2 ?v cc ? +5v supply input pin3 ? gnd ? ground reference for all signals pin 4 ?pfi ?power-fail input. this is the noninverting input to the power-fail com- parator. when pfi is less than 1.25v, pfo goes low. connect pfi to gnd or v out when not used. pin 5 ?pfo ?power-fail output. pin 6 ?wdi ?watchdog input. wdi is a three level input. if wdi remains high or low for 1.6sec, the internal watchdog timer triggers a reset. if wdi is left floating or connected to a high-impedance tri-state buffer, the watchdog feature is disabled. the internal watchdog timer clears when- ever reset is asserted. pin 7 for sp690a/692a/802 only ?reset (active low)?reset output. reset out- put goes low whenever v cc falls below the reset threshold or whenever wdi remains high or low longer than 1.6 seconds. reset remains low for 200ms after v cc crosses the reset threshold voltage on power-up or after being trig- gered by wdi. pin 7 for sp805 only ?reset (active high) reset output is the inverse of reset; when reset is asserted, the reset output voltage = v cc or v batt , whichever is higher. pin 8 ?v batt ? backup-battery input. when v cc falls below the reset threshold, v batt will be switched to v out if v batt is 20mv greater than v cc . when v cc rises 20mv above v batt , v out will be reconnected to v cc . the 40mv hysteresis prevents repeated switching if v cc falls slowly. figure 10. pinout f igure 11. internal block diagram v out v cc gnd pfi v batt reset (reset)* wdi pfo 1 2 3 4 5 6 7 8 *( ) sp805 only 1.25v 0.8v 3.5v 1.25v ba ttery-switchover circuitry pfi wdi v cc v batt reset generator v out reset (reset)* pfo wa tchdog timer *( ) sp805 only
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 5 v cc supply current vs. temperature (normal mode) battery supply current vs. temperature (backup mode) 51 47 43 39 35 31 27 23 19 -60 -30 0 30 60 90 120 150 v cc current ( a) temperature deg. c 2.9 2.4 1.9 1.4 0.9 0.4 -0.1 v batt current ( a) -60 temperature deg. c -40 -20 0 20 40 60 80 100 120 140 v cc =5v v batt =2.8v v cc =0v v batt =2.8v typical performance characteristics -60 -30 0 30 60 90 120 150 temperature deg. c pfi threshold vs. temperature 1.256 1.254 1.252 1.250 1.248 1.246 pfi threshold (v) v cc =5v v batt =0 no load on pfo v batt to v out on resistance vs. temperature v cc to v out on resistance vs. temperature 15 10 5 0 resistance (ohms) -60 -30 0 30 60 90 120 150 temperature deg. c 0.9 0.8 0.7 0.6 0.5 0.4 0.3 resistance (ohms) temperature deg. c v batt =2.8v v batt =4.5v v cc =0v v batt =2v reset threshold vs. temperature 4.70 4.69 4.68 4.67 4.66 4.65 4.64 4.63 4.62 4.61 4.60 reset threshold (v) temperature deg. c v batt =0v power down v cc =5v v batt =0v reset output resistance vs. temperature reset delay vs. temperature 600 500 400 300 200 100 0 resistance (ohms) -60 -30 0 30 60 90 120 150 temperature deg. c 212 210 208 206 204 202 200 reset delay (ms) -60 -30 0 30 60 90 120 150 temperature deg. c v cc =5v,v batt =2.8v soucing current v cc =0v to 5v step, v batt =2.8v v cc =0v,v batt =2.8v sink current ie+2 ie+1 ie+0 ie-1 ie-2 ie-3 ie-4 ie-5 ie-6 ie-7 ie-8 v batt current( a) log scale .0000 5.000 v cc (0.5v/div) battery current vs. v cc voltage v batt =2.8v sp690a -60 -30 0 30 60 90 120 150 -60 -30 0 30 60 90 120 150 (25 o c, unless otherwise noted)
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 6 figure 1. v cc to v out vs. output current figure 3a. sp690a reset output voltage vs. supply voltage figure 2. v batt to v out vs. output current figure 3b. circuit for the sp690a/802l reset output voltage vs. supply voltage gnd reset v cc 330pf v cc 2k ? reset v batt = 0v t a = +25 c voltage drop(mv) 1 10 100 1000 iout (ma) v cc =4.5v v batt =0v slope=0.6 ? voltage drop(mv) 1 10 100 iout (ma) v batt =4.5v v cc =0v slope=5 ? figure 4a. sp805l reset output voltage vs. supply voltage figure 4b. circuit for the sp805 reset output voltage vs. supply voltage gnd reset v cc 330pf v cc 10k ? v batt 1000 100 10 1 1000 100 10 1 reset 0v v cc v batt = 0v t a = 25 c o 0v 2v div reset 5v v cc 0v 0v 2v div 1sec/div 1sec/div
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 7 figure 5a. sp690a reset response time figure 5b. circuit for the sp690a/802l reset response time gnd reset v cc 30pf v cc 10k ? t a = +25 c figure 6a. sp805l reset response time figure 6b. circuit for the sp805 reset response time gnd reset v cc 330pf v cc 10k ? v batt figure 7b. circuit for the power-fail comparator response time (fall) figure 7a. power-fail comparator response time (fall) 30pf 1k ? pfo +1.25v +5v pfi v cc = +5v t a = +25 c reset v cc +4v +5v +5v 0v reset v cc 0v +5v +4v +4v +1.3v +1.2v pfi v cc = 5v v batt = 0v pfo 0v 5v 2 s/div 2 s/div 500ns/div
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 8 figure 8a. power-fail comparator response time (rise) figure 8b. circuit for the power-fail comparator response time (rise) 30pf 1k ? pfo +1.25v +5v pfi v cc = +5v t a = +25 c figure 9. timing diagram v cc reset* pfo v out 0v +5v 3.0v 0v 0v 0v +5v +5v +5v t rs 3.0v 0v +5v reset** v batt = pfi = 3.0v *sp690a/692a/802l/802m **sp805l/805m +1.3v +1.2v pfi v cc = 5v v batt = 0v 3v pfo 0v 2 s/div
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 9 theory of operation the sp690a/692a/802l/802m/805l/805m microprocessor ( p) supervisory circuits monitor the power supplied to digital circuits such as microprocessors, microcontrollers, or memory. the series is an ideal solution for portable, battery-powered equipment that requires power supply monitoring. implementing this series will reduce the number of components and overall complexity. the watchdog functions of this product family will continuously oversee the operational status of a system. the operational features and benefits of the sp690a/692a/802l/802m/805l/805m are described in more detail below. reset output the microprocessor's ( p's) reset input starts the p in a known state. when the p is in an unknown state, it should be held in reset. the sp690a/sp692a/sp802 assert reset during power-up and prevent code execution errors during power-down or brownout conditions. on power-up, once v cc reaches 1v, reset is guaranteed to be a logic low. as v cc rises, reset remains low. when v cc exceeds the reset threshold, reset will remain low for 200ms, figure 9 . if a brownout condition occurs and v cc dips below the reset threshold, reset is triggered. each time reset is triggered, it stays low for the reset pulse width interval. if a brownout condition interrupts a previously initiated reset pulse, the reset pulse continues for another 200ms. on power-down, once v cc goes below the threshold, reset is guaranteed to be logic low until v cc drops below 1v. reset is also triggered by a watchdog timeout. if wdi remains either high or low for a period that exceeds the watchdog timeout period (1.6 sec), reset pulses low for 200ms. as long as reset is asserted, the watchdog timer remains clear. when reset comes high, the watchdog resumes timing and must be serviced within 1.6sec. if wdi is tied high or low, a reset pulse is triggered every 1.8sec (t wd plus t rs ). features the sp690a/692a/802l/802m/805l/805m provide four key functions: 1. a battery backup switching for cmos ram, cmos microprocessors, or other logic. 2. a reset output during power-up, power-down and brownout conditions. 3. a reset pulse if the optional watchdog timer has not been toggled within a specified time. 4. a 1.25v threshold detector for power-fail warning, low battery detection, or to monitor a power supply other than +5v. the parts differ in their reset-voltage threshold levels and reset outputs. the sp690a/802l/ 805l generate a reset when the supply voltage drops below 4.65v. the sp692a/802m/805m generate a reset below 4.40v. the sp690a/692a/802l/802m/805l/805m are ideally suited for applications in automotive systems, intelligent instruments, and battery- powered computers and controllers. all designs into an environment where it is critical to monitor the power supply to the p and it? related digital components will find the ssp690a/692a/802l/802m/805l/805m ideal. figure 12. typical operating circuit gnd gnd reset nmi i/o line v cc reset pfo wdi v out bus v cc gnd v batt r 2 r 1 unregulated regulated +5v v cc 0.1 f pfi dc lithium battery 3.6v p cmos ram
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 10 the sp805l/m active-high reset output is the inverse of the sp690a/sp692a/sp802 re- set output, and is valid with v cc down to 1v. some p's, such as intel's 80c51, require an active-high reset pulse. watchdog input the watchdog circuit monitors the p's activity. if the p does not toggle the watchdog input (wdi) within 1.6sec, a reset pulse is triggered. the internal 1.6sec timer is cleared by either a reset pulse or by floating the wdi input. as long as reset is asserted or the wdi input is floating, the timer remains cleared and does not count. as soon as reset is released and wdi is driven high or low, the timer starts counting. it can detect pulses as short as 50ns. power-fail comparator the power-fail comparator can be used as an under-voltage detector to signal the failing of a power supply (it is completely separate from the rest of the circuitry and does not need to be dedicated to this function). the pfi input is compared to an internal 1.25v reference. if pfi is less than 1.25v, pfo goes low. the external voltage divider drives pfi to sense the unregulated dc input to the +5v regulator. the voltage-divider ratio can be chosen such that the voltage at pfi falls below 1.25v just before the +5v regulator drops out. pfo then triggers an interrupt which signals the p to prepare for power-down. when v batt connects to v out , the power-fail comparator is turned off and pfo is forced low to conserve backup-battery power. backup-battery switchover in the event of a brownout or power failure, it may be necessary to preserve the contents of ram. with a backup battery installed at v batt , the ram is assured to have power if v cc fails. as long as v cc exceeds the reset threshold, v out connects to v cc through a 0.6 ? pmos power switch. once v cc falls below the reset threshold, v cc or v batt , whichever is higher, switches to v out . v batt connects to v out through a 5 ? switch only when v cc is below the reset threshold and v batt is greater than v cc . when v cc exceeds the reset threshold, it is connected to v out , regardless of the voltage applied to v batt figure 13 . during this time, the diode (d1) between v batt and v out will conduct current from v batt to v out if v batt is more than .6v above v out . when v batt connects to v out , backup mode is activated and the internal circuitry will be pow- ered from the battery figure 14 . when v cc is just below v batt , in the backup mode the current drawn from v batt will be typically 30 a. when v cc drops to more than 1v below v batt , the internal switchover comparator shuts off and the supply current falls to less than 0.6 a. reset threshold = 4.65v in sp690a/802l/805l reset threshold = 4.40v in sp692a/802m/805m figure 13. backup-battery switchover block diagram sw1 d1 d2 d3 sw2 v batt v cc gnd v out n o i t i d n o c1 w s2 w s v c c d l o h s e r h t t e s e r >n e p od e s o l c v c c d n a d l o h s e r h t t e s e r < v c c v > t t a b n e p od e s o l c v c c d n a d l o h s e r h t t e s e r < v c c v < t t a b d e s o l cn e p o
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 11 l a n g i ss u t a t s v c c v m o r f d e t c e n n o c s i d t u o v t u o v o t d e t c e n n o c t t a b h g u o r h t 8 l a n r e t n i n a ? h c t i w s s o m p v t t a b v o t d e t c e n n o c t u o t n e r r u c . s i y r e t t a b e h t m o r f n w a r d 6 . 0 n a h t s s e l s a g n o l s a , a v c c v < t t a b . v 1 - i f p s i r o t a r a p m o c l i a f - r e w o p . d e l b a s i d o f pw o l c i g o l t e s e rw o l c i g o l t e s e r) y l n o 5 0 8 p s ( h g i h c i g o l i d wd e l b a s i d s i r e m i t g o d h c t a w using a high capacity capacitor as a backup power source v batt has the same operating voltage range as v cc , and the battery-switchover threshold volt- ages are typically +20mv centered at v batt , allowing use of a capacitor and a simple charging circuit as a backup source (see f igure 16) . if v cc is above the reset threshold and v batt is 0.5v above v cc , current flows to vout and v cc from v batt until the voltage at v batt is less than 0.5v above v cc . leakage current through the capacitor charging diode and the sp690a/sp802l/sp805l internal power diode eventually discharges the capacitor to v cc . also, if v cc and v batt start from 0.5v above the reset threshold and power is lost at v cc , the capacitor on v batt discharges through v cc until v batt reaches the reset threshold; the sp690a/sp802l/sp805l then switches to battery-backup mode. figure 15. allowable backup-battery voltages figure 14. input and output status in battery-backup mode. to enter the battery-backup mode, v cc must be less than the reset threshold and less than v batt . figure 16. backup power source using high capacity capacitor with sp690a/802l/805l and a +5v 5% supply figure 17. backup power source using high capacity capacitor with sp692a/802m/805m and a +5v 10% supply v cc +5v gnd v batt v out reset connect to static ram to p 0.1f connect (reset)* *( ) sp805l only v cc +5v gnd v batt v out reset connect to static ram to p 100k ? 0.1f connect (reset)* *( ) sp805m only t r a p r e b m u nr e b m u n r e b m u n r e b m u nr e b m u n m u m i x a m y r e t t a b - p u k c a by r e t t a b - p u k c a b y r e t t a b - p u k c a b y r e t t a b - p u k c a by r e t t a b - p u k c a b ] v [ e g a t l o v] v [ e g a t l o v ] v [ e g a t l o v ] v [ e g a t l o v] v [ e g a t l o v a 0 9 6 p s l 2 0 8 p s l 5 0 8 p s 0 8 . 4 a 2 9 6 p s m 2 0 8 p s m 5 0 8 p s 5 5 . 4
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 12 allowable backup power-source batteries lithium batteries work very well as backup batteries due to very low self-discharge rate and high energy density. single lithium batteries with open-circuit voltages of 3.0v to 3.6v are ideal. any battery with an open-circuit voltage less than the minimum reset threshold plus 0.3v can be connected directly to the v batt input of this series with no additional circuitry; see figure 12. however, batteries with open- circuit voltages that are greater than this value cannot be used for backup, as current is sourced into v out through the diode (d1 in figure 13) when v cc is close to the reset threshold. operation without a backup power source if a backup power source is not used, ground v batt and connect v out to v cc . since there is no need to switch over to any backup power source, v out does not need to be switched. a direct connection to v cc eliminates any voltage drops across the switch which may push v out below v cc . replacing the backup battery the backup battery can be removed while v cc remains valid, without danger of triggering reset/reset. as long as v cc stays above the reset threshold, battery-backup mode cannot be entered. adding hysteresis to the power-fail comparator hysteresis adds a noise margin to the power-fail comparator and prevents repeated triggering of pfo when v in is close to its trip point. figure 18 shows how to add hysteresis to the power-fail comparator. select the ratio of r 1 and r 2 such that pfi sees 1.25v when v in falls to its trip point (v trip ). r 3 adds the hysteresis. it will typically be an order of magnitude greater (about 10 times) than r 1 or r 2 . the current through r 1 and r 2 should be at least 1 a to ensure that the 25na (max) pfi input current does not shift the trip point. r 3 should be larger than 10k ? so it does not load down the pfo pin. capacitor c1 adds additional noise rejection. monitoring a negative voltage the power-fail comparator can be used to monitor a negative supply rail using the circuit of figure 19. when the negative rail is valid, pfo is low. when the negative supply voltage drops, pfo goes high. this circuit's accuracy is affected by the pfi threshold tolerance, the v cc voltage, and the resistors, r1 and r2. figure 18. adding hysteresis to the power-fail comparator pfi pfo r 3 *c 1 r 2 r 1 v in connect to p v cc +5v gnd pfo v in +5v v l v h v trip 0v 0v *optional v trip = r 2 r 1 + r 2 v h = r 2 || r 3 r 1 + r 2 || r 3 1.25 r 2 = v l - 1.25 r 1 5.0 - 1.25 r 3 + 1.25 1.25
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 13 interfacing to microprocessors with bidirectional reset pins microprocessors with bidirectional reset pins, such as the motorola 68hc11 series, can con- tend with this series' reset output. if, for example, the reset output is driven high and the p wants to pull it low, indeterminate logic levels may result. to correct this, connect a 4.7k ? resistor between the reset output and the p reset i/o, as in figure 20 . buffer the reset output to other system components. figure 19. monitoring a negative voltage figure 20. interfacing to microprocessors with bidirectional reset i/o pfi pfo r 2 r 1 v cc +5v gnd pfo v- +5v *v trip 0v 0v 5.0 - 1.25 r 1 1.25 - v trip r 2 v- = *v trip is a negative voltage v cc +5v gnd v cc +5v gnd reset reset 4.7k ? p buffered reset connects to system components
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 14 index area b n 1 23 n/2 c d1 ea eb e symbol min nom max a- - 0.21 a1 0.15 - - a2 0.115 0.13 0.195 b 0.014 0.018 0.022 b2 0.045 0.06 0.07 b3 0.3 0.039 0.045 c 0.008 0.01 0.014 d 0.355 0.365 0.4 d1 0.005 - - e 0.3 0.31 0.325 e1 0.24 0.25 0.28 e ea eb - - 0.43 l 0.115 0.13 0.15 note: dimensions in (mm) .100 bsc .300 bsc 8 pin pdip jedec ms-001 (ba) variation e e1 d a l a2 a1 b b2 e b3 c package: 8 pin pdip
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 15 a a1 a2 side view seating plane section b-b with plating symbol min nom max a1.35- 1.75 a1 0.1 - 0.25 a2 1.25 - 1.65 b0.31- 0.51 c0.17- 0.24 d e e1 e l0.4-1 .27 l1 l2 ?0o-8o ?1 5o - 15o note: dimensions in (mm) 8 pin nsoic jedec mo-012 (aa) variation 4.90 bsc 6.00 bsc 3.90 bsc 1.27 bsc 1.04 ref 0.25 bsc gauge plane l1 l ? 1 ? seating plane l2 view c to p view b see view c b b e e/2 e1 index area (d/2 x e1/2) e1/2 d 1 e c base metal b package: 8 pin nsoic
date: 1/19/05 sp690a/692a low power microprocessor supervisory with battery switch-over ? copyright 2005 si pex corporation 16 ordering information model temperature range package types sp690acn........................................................0 c to +70 c.....................................................8-pin nsoic sp690acn/tr...................................................0 c to +70 c.....................................................8-pin nsoic sp690acp........................................................0 c to +70 c.........................................................8-pin pdip sp690aen......................................................-40 c to +85 c.....................................................8-pin nsoic sp690aen/tr.................................................-40 c to +85 c.....................................................8-pin nsoic sp690aep.......................................................-40 c to +85 c.......................................................8-pin pdip sp692acn........................................................0 c to +70 c......................................................8-pin nsoic sp692acn/tr..................................................0 c to +70 c......................................................8-pin nsoic sp692acp........................................................0 c to +70 c.........................................................8-pin pdip sp692aen......................................................-40 c to +85 c.....................................................8-pin nsoic sp692aen/tr................................................-40 c to +85 c.....................................................8-pin nsoic sp692aep.......................................................-40 c to +85 c.......................................................8-pin pdip sp802lcn........................................................0 c to +70 c......................................................8-pin nsoic sp802lcn/tr..................................................0 c to +70 c......................................................8-pin nsoic sp802lcp........................................................0 c to +70 c.........................................................8-pin pdip sp802len.......................................................-40 c to +85 c....................................................8-pin nsoic sp802len/tr.................................................-40 c to +85 c....................................................8-pin nsoic sp802lep.......................................................-40 c to +85 c.......................................................8-pin pdip sp802mcn.......................................................0 c to +70 c......................................................8-pin nsoic sp802mcn/tr.................................................0 c to +70 c......................................................8-pin nsoic sp802mcp.......................................................0 c to +70 c.........................................................8-pin pdip sp802men......................................................-40 c to +85 c....................................................8-pin nsoic sp802men/tr................................................-40 c to +85 c....................................................8-pin nsoic sp802mep......................................................-40 c to +85 c.......................................................8-pin pdip sp805lcn........................................................0 c to +70 c......................................................8-pin nsoic sp805lcn/tr..................................................0 c to +70 c......................................................8-pin nsoic sp805lcp........................................................0 c to +70 c.........................................................8-pin pdip sp805len.......................................................-40 c to +85 c....................................................8-pin nsoic sp805len/tr.................................................-40 c to +85 c....................................................8-pin nsoic sp805lep.......................................................-40 c to +85 c.......................................................8-pin pdip sp805mcn.......................................................0 c to +70 c......................................................8-pin nsoic sp805mcn/tr..................................................0 c to +70 c......................................................8-pin nsoic sp805mcp.......................................................0 c to +70 c.........................................................8-pin pdip sp805men......................................................-40 c to +85 c....................................................8-pin nsoic sp805men/tr................................................-40 c to +85 c....................................................8-pin nsoic sp805mep......................................................-40 c to +85 c.......................................................8-pin pdip corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 /tr = tape and reel pack quantity 2,500 for nsoic. available in lead free packaging. to order add ?-l? suffix to part number. example: sp802lcn/tr = standard; sp802lcn-l/tr = lead free click here to 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